Verification of Advanced High Performance Bus Arbiter using System Verilog Assertion

With the fanatically improvement in electronics interconnection technologies, Arbiter is required for high performance buses. Arbiters subsist in almost every logic design. In many designs a large number of requesters must access a same resource. An arbiter is used to arbitrate how the resource is shared amongst the multiple requesters. The arbitration plays a captious role to determine the performance of bus based system, as it assign precedence with which processors is grant the access to the shared communication resources. In this paper, Round robin arbitration is used for scheduling and verified by using (SVA) SystemVerilog Assertion as it is widely used verification techniques to enhance the verification quality and reduce the debugging time of complex designs in order to speedup the verification process. Here, Advanced High Performance Bus (AHB) Arbiter is designed in verilog language. This design is then verified using SVA binding construct in ModelSim. Binding allows verification engineers to add assertions to design without touching the design files. KeywordsVerification, Arbiter, SVA, Bind, Assertion.